For a Complementary Metal-Oxide-Semiconductor (CMOS) image sensor (CIS), some typical circuits such like a slop Analog-to-Digital converter, or a ramp generator which has big size and is shared with multi-columns to readout large array in parallel is not preferred for a readout circuit of the CIS in a miniature size application. For example, a scribe line testing application or an Internet of Thing application. In addition, a typical CIS requires a plurality of timing control signals to control column and row circuit function, and each signal needs a lot of registers to implement a rising event or a falling event. However, this architecture involving a lot of registers lacks of flexibility and limits the capability. Therefore, a novel architecture is desired to solve the aforementioned problem.